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> as the P6 demonstrated complicated CISC addressing modes can be trivially decomposed and issued to a superscalar RISC core.

Doing that required a very large amount of area and transistors in its early days. So much that very smart people thought that the extra area requirements would kill that approach. It still does take a large amount of area, but less and less relative to the available die. Moore's law basically blew past any concerns there.

But it wasn't always obvious that that would be the case.

https://arstechnica.com/features/1999/10/rvc/



It was obvious enough when 68k was still in the market though. The P6 shipped in 1995.


AMD was there in 1996, barely couple of months behind Intel with 4.3M transistors am29000 based K5.




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